View LTC1414_290812.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Final Electrical Specifications
LTC1414 14-Bit, 2.2Msps, Sampling A/D Converter
August 1998
FEATURES
s s s s s s s s s s
DESCRIPTION
The LTC (R)1414 is a 14-bit, 2.2Msps, sampling A/D converter which draws only 175mW from 5V supplies. This high performance ADC includes a high dynamic range sample-and-hold, a precision reference and requires no external components. The LTC1414's high performance sample-and-hold has a full-scale input range of 2.5V. Outstanding AC performance includes 80dB S/(N + D) and 95dB SFDR with a 100kHz input. The performance remains high at the Nyquist input frequency of 1.1MHz with 78dB S/(N + D) and 86dB SFDR. The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 40MHz bandwidth. The 70dB common mode rejection can eliminate ground loops and common mode noise by measuring signal differentially from the source The ADC has a microprocessor compatible, 14-bit parallel output port. There is no pipline delay in the conversion results.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Sample Rate: 2.2Msps 80dB S/(N + D) and 95dB SFDR at 100kHz 78dB S/(N + D) and 86dB SFDR at Nyquist Power Dissipation: 175mW on 5V Supplies External or Internal Reference Operation No Pipeline Delay True Differential Inputs Reject Common Mode Noise 2.5V Bipolar Input Range 40MHz Full Power Bandwidth Sampling 28-Pin Narrow SSOP Package
APPLICATIONS
s s s s s s
Telecommunications Digital Signal Processing Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectrum Analysis Imaging Systems
TYPICAL APPLICATION
5V 10F AVDD LTC1414 DVDD OVDD OPTIONAL 3V LOGIC SUPPLY
Effective Bits and Signal-to-Noise + Distortion vs Input Frequency
14 13 12 11 86 80 74 68
EFFECTIVE BITS
AIN + S/H AIN
-
14 14-BIT ADC OUTPUT BUFFERS
* * *
D13 (MSB)
10 9 8 7 6 5 4
D0 (LSB)
4.0625V COMP 10F VREF 1F VSS 10F - 5V AGND DGND OGND
1414 TA01
BUFFER 2k BUSY CONVST
2.5V REFERENCE
TIMING AND LOGIC
3 2 1k
fSAMPLE = 2.2MHz 10k 100k 1M INPUT FREQUENCY (Hz) 10M
1414 TA02
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
U
U
S/(N + D) (dB)
1
LTC1414
ABSOLUTE MAXIMUM RATINGS
AVDD = OVDD = DVDD = VDD (Notes 1, 2)
PACKAGE/ORDER INFORMATION
TOP VIEW AIN+ AIN- VREF REFCOMP AGND D13 (MSB) D12 D11 D10 1 2 3 4 5 6 7 8 9 28 AVDD 27 AGND 26 VSS 25 BUSY 24 CONVST 23 DGND 22 DVDD 21 OVDD 20 D0 19 D1 18 D2 17 D3 16 D4 15 D5
Supply Voltage (VDD) ................................................. 6V Negative Supply Voltage (VSS)................................. - 6V Total Supply Voltage (VDD to VSS) .......................... 12V Analog Input Voltage (Note 3) ......................... (VSS - 0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 4) ..........(VSS - 0.3V) to 10V Digital Output Voltage ........ (VSS - 0.3V) to (VDD + 0.3V) Power Dissipation .............................................. 500mW Operating Temperature Range ..................... 0C to 70C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1414CGN
D9 10 D8 11 D7 12 D6 13 OGND 14
GN PACKAGE 28-LEAD PLASTIC SSOP
TJMAX = 110C, JA = 110C/ W
Consult factory for Industrial, Military and A grade parts.
CO VERTER CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Full-Scale Error Full-Scale Tempco (Note 8) (Note 7) CONDITIONS
With internal reference (Notes 5, 6)
MIN
q q q q
LTC1414 TYP 0.75 0.75 5 10 5 15 1
MAX 2.0 1.75 20 24 60 25
UNITS Bits LSB LSB LSB LSB LSB LSB ppm/C ppm/C
13
Internal Reference External Reference = 2.5V Internal Reference External Reference = 2.5V
A ALOG I PUT
SYMBOL PARAMETER VIN IIN CIN tACQ tAP tjitter CMRR
(Note 5)
CONDITIONS 4.75V VDD 5.25V, - 5.25V VSS - 4.75V Between Conversions During Conversions
q q q
MIN
TYP 2.5
MAX 1
UNITS V A pF pF
Analog Input Range (Note 9) Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio
8 4 40 -1 3 100
psRMS dB
- 2.5V < (AIN-
= AIN+) < 2.5V
70
2
U
W
U
U
WW
W
U
U
U
ns ns
LTC1414
DY A IC ACCURACY
SYMBOL PARAMETER S/(N + D) Signal-to-Noise Plus Distortion Ratio THD SFDR IMD Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth
I TER AL REFERE CE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance COMP Output Voltage CONDITIONS IOUT = 0 IOUT = 0 4.75V VDD 5.25V - 5.25V VSS - 4.75V
IOUT 0.1mA
DIGITAL I PUTS AND OUTPUTS
SYMBOL PARAMETER VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage D13 to D0 Hi-Z Output Capacitance D13 to D0 Output Source Current Output Sink Current
POWER REQUIRE E TS
SYMBOL PARAMETER VDD VSS IDD ISS PD Positive Supply Voltage Negative Supply Voltage Positive Supply Current Negative Supply Current Power Dissipation
UW
U
U
U
WU
U
(Note 5)
CONDITIONS 100kHz Input Signal 1.1MHz Input Signal 100kHz Input Signal, First 5 Harmonics 1.1MHz Input Signal, First 5 Harmonics 100kHz Input Signal 1.1MHz Input Signal, First 5 Harmonics fIN1 = 29.37kHz, fIN2 = 32.446kHz S/(N + D) 74dB MIN TYP 80 78 - 95 - 84 95 86 - 86 40 1.8 MAX UNITS dB dB dB dB dB dB dB MHz MHz
U
(Note 5)
MIN 2.480 TYP 2.500 15 0.01 0.01 2 4.06 MAX 2.520 UNITS V ppm/C LSB/ V LSB/ V k V
IOUT = 0
(Note 5)
MIN
q q q
CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD VDD = 4.75V, IO = - 10A VDD = 4.75V, IO = - 200A VDD = 4.75V, IO = 160A VDD = 4.75V, IO = 1.6mA VOUT = 0V to VDD, CS High CS High (Note 9) VOUT = 0V VOUT = VDD
TYP
MAX 0.8 10
UNITS V V A pF V V
2.4
1.2 4.74
q q q q
4.0 0.05 0.10 0.4 10 15 - 10 10
V V A pF mA mA
(Note 5)
CONDITIONS (Note 10) (Note 10) CS High CS High
q q
MIN 4.75 - 4.75
TYP
MAX 5.25 - 5.25
UNITS V V mA mA mW
12 23 175
16 30 230
3
LTC1414
TI I G CHARACTERISTICS
SYMBOL fSAMPLE(MAX) tCONV tACQ tTHROUGHPUT t1 t2 t3 t4 t5 t6 PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time
The q denotes specifications which apply over the full operating temperature range; all other limits and typicals TA = 25C. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND and AGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or above VDD without latchup. Note 4: When these pin voltages are taken below VSS, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, VSS = - 5V, fSAMPLE = 2.2MHz and tr = tf = 5ns unless otherwise specified.
TI I G DIAGRA
CONVST t1 BUSY t2 DATA DATA (N - 1) DB13 TO DB0 DATA N DB13 TO DB0 DATA (N + 1) DB13 TO DB0 t3
4
W
UW
UW
(Note 5)
CONDITIONS
q q q q
MIN 2.2 220
TYP 330 40 370 10 20
MAX 400 100 454
UNITS MHz ns ns ns ns ns ns ns ns
Throughput Time (Acquisition + Conversion) CONVST to BUSY Delay Data Ready Before BUSY Delay Between Conversions CONVST Low Time CONVST High Time Aperture Delay of Sample-and-Hold (Note 10) (Note 11) (Note 11) CL = 25pF
q q q
100 40 40 -1
ns
Note 6: Linearity, offset and full-scale specifications apply for a singleended AIN+ input with AIN- grounded. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from - 0.5LSB when the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: The falling CONVST edge starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For best results ensure that CONVST returns high either within 225ns after the start of the conversion or after BUSY rises.
tCONV t4 t5
1414 TD
LTC1414
PIN FUNCTIONS
A IN+ (Pin 1): Positive Analog Input. 2.5V input range when AIN- is grounded. 2.5V differential if AIN- is driven differentially with AIN+. AIN- (Pin 2): Negative Analog Input. Can be grounded or driven differentially with AIN+. VREF (Pin 3): 2.5V Reference Output. REFCOMP (Pin 4): 4.06V Reference Bypass Pin. Bypass to AGND with 10F ceramic or 10F tantalum in parallel with 0.1F ceramic. AGND (Pin 5): Analog Ground. D13 to D6 (Pins 6 to 13): Data Outputs. OGND (Pin 14): Digital Ground for the Output Drivers. Tie to AGND D5 to D0 (Pins 15 to 20): Data Outputs. OVDD (Pin 21): Positive Supply for the Output Drivers. Tie to Pin 28 when driving 5V logic. For 3V logic, tie to supply of the logic being driven. DVDD (Pin 22): 5V Positive Supply. Tie to Pin 28. DGND (Pin 23): Digital Ground. Tie to AGND. CONVST (Pin 24): Conversion Start Signal. This active low signal starts a conversion on its falling edge. BUSY (Pin 25): The BUSY Output Shows the Converter Status. It is low when a conversion is in progress. VSS (Pin 26): - 5V Negative Supply. Bypass to AGND with 10F ceramic or 10F tantalum in parallel with 0.1F ceramic. AGND (Pin 27): Analog Ground. AVDD (Pin 28): 5V Positive Supply. Bypass to AGND with 10F ceramic or 10F tantalum in parallel with 0.1F ceramic.
FUNCTIONAL BLOCK DIAGRA
AIN+ CSAMPLE AIN- 2k VREF 2.5V REF ZEROING SWITCHES AVDD DVDD VSS
REF AMP
REFCOMP (4.06V) AGND DGND INTERNAL CLOCK SUCCESSIVE APPROXIMATION REGISTER
W
U
U
U
U
U
CSAMPLE
+
14-BIT CAPACITIVE DAC COMP
-
OVDD 14 OUTPUT LATCHES * * * D13 D0 OGND CONTROL LOGIC
1414 BD
CONVST
BUSY
5
LTC1414
APPLICATIONS INFORMATION
Driving the Analog Input The differential analog inputs of the LTC1414 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN- input is grounded). The A IN+ and AIN- inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sampleand-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low then the LTC1414 inputs can be driven directly. As source impedance increases so will acquisition time (see Figure 1). For minimum acquisition time, with high source impedance, a buffer amplifier should be used. The only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 80ns for full throughput rate).
10
ACQUISITION TIME (s)
1
0.1
0.01 10 100 1k 10k SOURCE RESISTANCE () 100k
1414 F01
Figure 1. Acquisition Time vs Source Resistance
Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (<100) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 50MHz, then the output impedance at 50MHz must be less than 100. The Input Filtering The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1414 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 40MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input
LinearView is a trademark of Linear Technology Corporation.
6
U
W
U
U
second requirement is that the closed-loop bandwidth must be greater than 40MHz to ensure adequate smallsignal settling for full throughput rate. If slower op amps are used, more settling time can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC1414 will depend on the application. Generally applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC1414. More detailed information is available in the Linear Technology Databooks and on the LinearViewTM CD-ROM. LT(R)1223: 100MHz Video Current Feedback Amplifier. 6mA supply current. 5V to 15V supplies. Low noise. Good for AC applications. LT1227: 140MHz Video Current Feedback Amplifier. 10mA supply current. 5V to 15V supplies. Low noise. Best for AC applications. LT1229/LT1230: Dual and Quad 100MHz Current Feedback Amplifiers. 2V to 15V supplies. Low noise. Good AC specifications, 6mA supply current each amplifier. LT1360: 50MHz Voltage Feedback Amplifier. 3.8mA supply current. Good AC and DC specs. 5V to 15V supplies. 70ns settling to 0.5LSB. LT1363: 70MHz, 1000V/s Op Amps. 6.3mA supply current. Good AC and DC specifications. 60ns settling to 0.5LSB. LT1364/LT1365: Dual and Quad 70MHz, 1000V/s Op Amps. 6.3mA supply current per amplifier. 60ns settling to 0.5LSB.
LTC1414
APPLICATIONS INFORMATION
circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 2 shows a 500pF capacitor from AIN+ to ground and a 100 source resistor to limit the input bandwidth to 3.2MHz. The 500pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling glitch-sensitive circuitry. High quality capacitors and resistors should be used since poor quality components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. Input Range The 2.5V input range of the LTC1414 is optimized for low noise and low distortion. Most op amps also perform best over this same range, allowing direct coupling to the analog inputs and eliminating the need for special translation circuitry. Some applications may require other input ranges. The LTC1414 differential inputs and reference circuitry can accommodate other input ranges often with little or no additional circuitry. The following sections describe the reference and input circuitry and how they affect the input range.
100 INPUT 500pF 1 2 3 4 10F 5 AGND
LTC1414 * F02
AIN+
2.500V
AIN
-
LTC1414 VREF REFCOMP
10F R3 64k 4.0625V 4 REFCOMP
Figure 2. An RC Filter Reduces the ADC's 40MHz Bandwidth to 3.2MHz and Filters Out Wideband Noise Which May Be Present in the Input Signal
U
W
U
U
Internal Reference The LTC1414 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500V. It is connected internally to a reference amplifier and is available at VREF (Pin 3), see Figure 3. A 2k resistor is in series with the output so that it can be easily overdriven by an external reference or other circuitry. The reference amplifier multiplies the voltage at the VREF pin by 1.625 to create the required internal reference voltage. This provides buffering between the VREF pin and the high speed capacitive DAC. The reference amplifier compensation pin, REFCOMP (Pin 4) must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of 1F or greater. For the best noise performance, a 10F ceramic or 10F tantalum in parallel with a 0.1F ceramic is recommended. The VREF pin can be driven with a DAC or other means shown in Figure 4. This is useful in applications where the peak input signal amplitude may vary. The input span of the ADC can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. The filtering of the internal LTC1414 reference amplifier will limit the bandwidth and settling time of this circuit. A settling time of 5ms should be allowed after a reference adjustment.
3 VREF
R1 2k
BANDGAP REFERENCE
+
REFERENCE AMP
-
R2 40k
5 AGND
LTC1414
1414 F03
Figure 3. LTC1414 Reference Circuit
7
LTC1414
APPLICATIONS INFORMATION
1 ANALOG INPUT 2V TO 3V DIFFERENTIAL AIN+ AIN- LTC1414 LTC1450 2V TO 3V 3 VREF
2
4 10F 5
REFCOMP
AGND
1414 F04
Figure 4. Driving VREF with a DAC
OUTPUT CODE
Differential Inputs The LTC1414 has a unique differential sample-and-hold circuit that allows rail-to-rail inputs. The ADC will always convert the difference of AIN+ - (AIN-) independent of the common mode voltage. The common mode rejection holds up to extremely high frequencies, see Figure 5. The only requirement is that neither input can exceed the AVDD or AVSS power supply voltages. Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are independent of the common mode voltage, however, the bipolar zero error (BZE) will vary. The change in BZE is typically less than 0.1% of the common mode voltage. Dynamic performance is also affected by the common mode voltage. THD will degrade as the inputs approach either power supply rail, from -86dB with a common mode of 0V to -75dB with a common mode of 2.5V or -2.5V.
80 COMMON MODE REJECTION (dB) 70 60 50 40 30 20 10 0 1k 1M 10k 100k INPUT FREQUENCY (Hz) 10M
LTC1414 * F05
Figure 5. CMRR vs Input Frequency
8
U
W
U
U
Full-Scale and Offset Adjustment Figure 6 shows the ideal input/output characteristics for the LTC1414. The code transitions occur midway between successive integer LSB values (i.e., - FS + 0.5LSB, - FS + 1.5LSB, - FS + 2.5LSB,...FS - 2.5LSB, FS - 1.5LSB). The output is two's complement binary with 1LSB = FS - (- FS)/16384 = 5V/16384 = 305.2V.
011...111 011...110 011...101 000...000 111...111
100...010 100...001 100...000 -(FS - 1LSB) 0 INPUT RANGE
LTC1414 * F06
FS - 1LSB
Figure 6. LTC1414 Transfer Characteristics
In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error must be adjusted before full-scale error. Figure 7 shows the extra components required for full-scale error adjustment. Zero offset is achieved by adjusting the offset applied to the AIN- input. For zero offset error apply - 152V (i.e., - 0.5LSB) at AIN+ and adjust the offset at the AIN- input until the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. For full-scale adjustment, an input voltage of 2.499544V (FS - 1.5LSBs) is applied to AIN+ and R2 is adjusted until the output code flickers between 0111 1111 1111 10 and 0111 1111 1111 11. Board Layout and Bypassing To obtain the best performance from the LTC1414, a printed circuit board with a ground plane is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as
LTC1414
APPLICATIONS INFORMATION
possible. In particular, care should be taken not to run any digital line alongside an analog signal line or underneath the ADC. The analog input should be screened by AGND. High quality tantalum and ceramic bypass capacitors should be used at the VDD, VSS and VREF pins. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC1414 has differential inputs to minimize noise coupling. Common mode noise on the AIN+ and AIN- inputs will be reflected by the input CMRR. The AIN- input can be used as a ground sense for the AIN+ input; the LTC1414 will hold and convert the difference voltage between AIN+ and AIN-. The leads to AIN+ (Pin 1) and AIN- (Pin 2) should be kept as short as possible. In applications where this is not possible, the AIN+ and AIN- traces should be run side by side to equalize coupling.
-5V R1 50k
R5 R2 47k 50k R6 24k 10F
Figure 7. Offset and Full-Scale Adjust Circuit
1
AIN+ AIN- REFCOMP 4 10F AGND 5, 27 2
ANALOG INPUT CIRCUITRY
+ -
Figure 8. Power Supply Grounding Practice
U
W
U
U
A single point analog ground separate from the logic system ground should be established with an analog ground plane at AGND (Pin 5, 27) or as close as possible to the ADC (see Figure 8). The ADC's DGND (Pin 23) and all other analog grounds should be connected to this single analog ground point. No other digital grounds should be connected to this analog ground point. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and these traces should be as wide as possible. Excessive capacitive loading on the ADC's data output lines can generate large transient currents on the ADC supplies which may affect conversion results. In these cases, the use of digital buffers is recommended to isolate the ADC from the excessive loading.
R3 24k
ANALOG INPUT R4 100
1
AIN+ AIN - LTC1414
2
3
VREF
4
REFCOMP
5
AGND
LTC1414 * F07
LTC1414 VSS 26 10F AVDD 28 10F DVDD OVDD DGND OGND 20 21 23 14
DIGITAL SYSTEM
ANALOG GROUND PLANE
1414 F08
9
LTC1414
APPLICATIONS INFORMATION
Digital Interface The A/D converter has just one control input CONVST. Data is output on 14-bit parallel bus. An additional output BUSY indicates the converter status. Internal Clock The internal clock is factory trimmed to achieve a typical conversion time of 330ns and a maximum conversion time over the full operating temperature range of 400ns. No external adjustments are required. The guaranteed maximum acquisition time is 100ns. In addition, a throughput time (acquisition + conversion) of 454ns and a minimum sampling rate of 2.2Msps is guaranteed. Timing and Control The conversion start is controlled by the CONVST input. The falling edge of CONVST will start a conversion. Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output. BUSY is low during a conversion. The output data is updated at the end of the conversion as BUSY rises. Output data is updated coincident with the rising edge of BUSY. Data will be valid, and can be latched, 20ns after the rising edge of BUSY. Valid data can also be latched with the falling edge of BUSY or with the rising edge of CONVST. In the latter two cases the data latched will be for the previous conversion.
tCONV t4 CONVST t1 BUSY t2 DATA DATA (N - 1) DB13 TO DB0 DATA N DB13 TO DB0 DATA (N + 1) DB13 TO DB0 t3 t5
10
U
W
U
U
1414 F09
Figure 9. Timing Diagram
LTC1414
PACKAGE DESCRIPTION
0.015 0.004 x 45 (0.38 0.10) 0.0075 - 0.0098 (0.191 - 0.249) 0.016 - 0.050 (0.406 - 1.270) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP
U
Dimensions in inches (millimeters) unless otherwise noted.
GN Package 28-Lead Plastic SSOP Narrow (0.150)
(LTC DWG # 05-08-1641)
0.386 - 0.393* (9.804 - 9.982) 28 27 26 25 24 23 22 21 20 19 18 17 1615
0.033 (0.838) REF
0.229 - 0.244 (5.817 - 6.198)
0.150 - 0.157** (3.810 - 3.988)
1 0.053 - 0.069 (1.351 - 1.748)
23
4
56
7
8
9 10 11 12 13 14 0.004 - 0.009 (0.102 - 0.249)
0.008 - 0.012 (0.203 - 0.305)
0.025 (0.635) BSC
GN28 (SSOP) 0398
11
LTC1414
TYPICAL APPLICATIO U
2.2MHz, 14-Bit Sampling ADC
5V DIFFERENTIAL ANALOG INPUT -2.5V TO 2.5V 1 2 3 4 10F 5 AIN+ AIN- VREF REFCOMP AGND AVDD AGND LTC1414 VSS BUSY CONVST DGND 6 D13 (MSB) 7 D12 8 D11 9 D10 10 D9 11 D8 14-BIT PARALLEL BUS 12 D7 13 D6 14 OGND DVDD OVDD D0 D1 D2 D3 D4 D5 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0.1F 5V -5V 10F 10F 1F
1414 TA03
VREF OUT 2.5V
RELATED PARTS
PART NUMBER LTC1412 LTC1415 LTC1416 LTC1418 LTC1419 DESCRIPTION Low Power, 12-Bit 3Msps ADC Single 5V, 12-Bit 1.25Msps ADC Low Power, 14-Bit 400ksps ADC Very Low Power 14-Bit, 200ksps ADC Low Power 14-Bit, 800ksps ADC COMMENTS Nyquist Sampling, 150mW, 72dB SINAD Single Supply, 55mW Dissipation 5V Supplies, 75mW Dissipation 15mW, 5V Supply, Serial or Parallel I/O True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
1414i LT/TP 0898 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1998

▲Up To Search▲

Price & Availability of LTC1414

	To Download LTC1414 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .